This invention relates to the manufacture of MOS semiconductor devices and, more particularly, to improvements in the method of forming gate electrodes.
Recently, attempts to reduce MOS transistor size have been made in light of a demand for increasing density of integration of NMOS semiconductor integrated circuits. One approach in the case of a MOS transistor having a construction as shown in FIG. 1, which comprises a p-type semiconductor substrate 1 provided with a gate oxide film 2 and a gate electrode 3 both formed atop a principal substrate and a source 4 and a drain 5 both formed as an n.sup.+ -type diffusion layer in the substrate, is to reduce the length L of the gate electrode 3 to increase the integration density. In this case, however, reduction of the threshold voltage and what is called short-channel effect such as the punch-through phenomenon are liable to result. A well-known scaling method is effective to improve the above disadvantages. This method, however, dictates reduction of the supply voltage and also increase of the substrate density. Reduction of the supply voltage leads to reduction of the margin concerning the electric noise and fluctuations of the threshold voltage. Increase of the substrate density is likely to result in increased current leak in the sub-threshold region. The significance of these problems is increased as integration density is increased. Regarding punch-through it is said that this phenomenon can be hardly prevented even by the scaling method in case where the effective channel length is less than 0.8.mu..
A concave MOS transistor method is well known as a means for preventing the start channel affect. This method makes use of a construction as shown in FIG. 2, in which a p-type semiconductor substrate 1 is formed with a recess 6 in which a gate oxide film 2' and a gate electrode 3' are formed adjacent to source 4 and drain 5 constituted by an n.sup.+ -type diffusion layer. The effective channel length L' can be increased in this case to an extent enough to prevent the short-channel effect. According to this method, the effective channel length L' can be suitably selected by appropriately setting the depth of the recess, and, by doing so, can eliminate the need of varying the drain voltage or substrate density. In the prior art method of a concave MOS transistor, however, difficulties are encountered in obtaining self-alignment of the recess 6 and gate electrode 3', and it is necessary to provide a margin A adjacent to both sides of the recess 6 in order to compensate the misalignment, as shown in FIG. 3. This is, however, undesired from the standpoint of size reduction of the MOS transistor. For example, if it is necessary to provide a margin A of 0.5.mu., the total increase of the gate length is 1.mu., which is a significant drawback in view of increasing the integration density of the concave MOS LSI.